1. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the invention is in the field of pseudomorphic high electron mobility transistor structures.
2. Background Art
In many applications, it is desirable to reduce the “on-state” resistance of transistors, such as field effect transistors (FETs) and, more particularly, pseudomorphic high electron mobility transistors (PHEMTs), without compromising performance or reliability. By way of background, the on-state resistance of a PHEMT refers to the source to drain resistance as measured while the PHEMT is in an operating state.
Various methods have been attempted in the art in an effort to reduce the on-state resistance of PHEMT structures. One method attempts to reduce gate length to achieve reduced on-state resistance. However, since gate length reduction is currently at the limits of process capabilities, new photolithography processes and equipment will be required to further reduce gate length. In another method, source to drain spacing is minimized to reduce on-state resistance. However, catastrophic gate to drain leakage can occur if source to drain spacing is reduced too much. In yet another method to reduce on-state resistance, thickness of the Schottky layer, which is typically situated above a highly conductive channel layer in the PHEMT structure, is increased. However, although providing a minimal reduction in on-state resistance, increasing Schottky layer thickness can have the undesirably effect of significantly decreasing pinch-off voltage.
Thus, there is a need in the art for a PHEMT structure which provides reduced on-state resistance without compromising performance or reliability.